The interface trap density of an oxide layer-silicon carbide interface using a silicon carbide (SiC) substrate is some ten times higher than that of a silicon MOS transistor. This gives rise to the problem that a silicon carbide substrate-based MOSFET has about one-tenth the channel mobility of a silicon substrate-based MOSFET. Although a bulk SiC substrate having the crystal structure referred to as 4H—SiC has about twice the channel mobility of a bulk SiC substrate having the crystal structure referred to as 6H—SiC, an oxide layer/silicon carbide interface has a high number of defects interface trap density) and, therefore, has lower channel mobility. It should be possible to utilize the higher channel mobility of a bulk 4H—SiC substrate to reduce the On-resistance of a power MOSFET. However, because of the low channel mobility, the On-resistance of 4H—SiC is higher than that of 6H—SiC, so reducing the interface trap density of the 4H—SiC MOS structure is critically important for realizing a SiC MOSFET. Typically, SiC has a (0001) face, a (11-20) face and a (000-1) face. The oxidation rate in the case of the (11-20) face is some ten times higher than that of the (0001) face, and that of the (000-1) face is higher still. This is because the oxidation mechanism of Si and C differs depending on the plane orientation. Since, therefore, the optimum oxidation conditions and post-oxidation annealing conditions for decreasing the interface trap density at the oxidation layer/silicon carbide interface also differ depending on the plane orientation, it is necessary to optimize oxidation conditions and post-oxidation annealing conditions for each plane orientation. In the initial research, SiC MOSFETs were formed on the (0001) face, but the channel mobility of such devices was no higher than 10 cm2/Vs.
The recent literature describes channel mobility being improved to up to 110 cm2/Vs by reducing the interface trap density by using H2O (water) to form a gate insulation layer on the (11-20) face of SiC and then subjecting the layer to hydrogen annealing. However, the (11-20) face has lower dielectric breakdown field strength than the (0001) or (000-1) face, and is therefore disadvantageous for high-voltage-resistancehigh blocking voltage voltage power devices. Also, there are no reports of MOSFETs fabricated on the (000-1) face operating without the use of channel doping technology. The channel doping technology is not suitable for high-voltage-resistancehigh blocking voltageblocking voltage power devices, because although it improves channel mobility, leakage current flows more readily and voltage resistanceblocldng voltage decreases. The present invention provides a technology for forming on a (000-1) face having a higher dielectric breakdown voltage than a (11-20) face, an oxide layer/silicon carbide interface having higher channel mobility than a (0001) face.
With respect to the method of oxidizing the silicon carbide substrate and the subsequent heat-treatment method, there have already been a number of announcements and patent disclosures, described below.
JP-A HEI 9-199497, for example, discloses a method of improving a thermal oxidation layer of a SiC single-crystal substrate by following the oxidation step with an annealing step using hydrogen and an annealing step using inert gas to reduce hysteresis and flat band-shift. In particular, this publication describes a method in which the silicon carbide oxidation is followed by hydrogen annealing at 1000° C. This method relates to the (0001) face of a silicon carbide substrate, and does not describe anything relating to the (000-1) face. Moreover, a temperature of 1000° C. is too high, with the oxidation layer being reduced by the hydrogen, degrading the reliability of a device in which the oxidation layer is used as a gate layer.
JP-A HEI 10-112460 discloses a silicon carbide semiconductor device fabrication method in which, in order to reduce the interface trap density, a thermal oxidation layer is formed, subjected to less than two hours of annealing in an inert gas atmosphere, and then heat-treated at a low temperature in the range 300° C. to 500° C. in hydrogen or a gas containing hydrogen atoms such as in the form of water vapor. This is then followed by a cooling period, at least part of which takes place in a gaseous atmosphere containing hydrogen atoms. So, the disclosure describes a method in which the gate oxidation layer is formed and heat-treated at 300° C. to 500° C. in an atmosphere containing hydrogen atoms, but the method relates to the (0001) face of a silicon carbide substrate and teaches nothing relating to the (000-1) face. Also, the heat treatment temperature within the range 300° C. to 500° C. is too low for adequate heat-treatment.
JP-A HEI 11-31691 discloses a method of forming a thermal oxidation layer in a SiC semiconductor device in which the interface trap density following layer formation is reduced by, in a method of forming a thermal oxidation layer in which the layer is grown by a pyrogenic oxidation process by introducing hydrogen and oxygen, (1) using a hydrogen-oxygen mixture in which there is more hydrogen than oxygen, or (2) after oxidation, cooling in an atmosphere containing hydrogen atoms and using a cooling rate within the range 0.3 to 3° C./min, or (3) following oxidation and cooling, using an extraction temperature of not more than 900° C. While the disclosure does describe a method of cooling in an atmosphere containing hydrogen after the pyrogenic oxidation, the method relates to the (0001) face of a SiC substrate, and does not relate to the (000-1) face. Also, the described mixture ratio of hydrogen and oxygen used in the pyrogenic method is not optimal.
JP-A 2000-252461 describes a semiconductor device fabrication method in which one, two or more oxide and/or nitride gate insulation layers are formed on at least the topmost layer of a silicon carbide substrate and are then annealed at 600° C. to 1600° C. in an atmosphere that contains hydrogen. In this method, a good gate insulation layer/silicon carbide interface able to adequately stand up to actual use can be obtained by using hydrogen to terminate silicon or carbon tangling bonds that exist in the interface to thereby adequately reduce the interface trap density. While the disclosure describes the use of heat treatment in hydrogen after forming the oxide layer on the silicon carbide substrate, the method relates to the (0001) face of a SiC substrate and has no disclosure of a desirable hydrogen heat treatment method with respect to the (000-1) face.
U.S. Pat. No. 5,972,801 discloses a method for obtaining improved oxide layers and resulting improved performance from oxide-based devices. The method reduces defects in an oxide layer on a silicon carbide substrate by using a process in which the oxide layer is exposed to an oxidizing atmosphere at a temperature that is below the temperature at which silicon carbide would oxidize while high enough to enable the oxidizing source gas to diffuse in the oxide, and for a time that is not long enough to cause additional oxidation of the silicon carbide substrate but is sufficient to density the oxide layer and improve the characteristics of the interface between the oxide layer and the substrate. The method describes treating the formed gate oxide layer at 600° C. to 1000° C. in an atmosphere containing water vapor, but this water vapor is produced not by the reaction of H2 gas and O2 gas, but by heating pure water. Moreover, the method as described does not relate to formation of a gate oxide layer on the (000-1) face followed by heat-treatment of the layer.
With respect to the (000-1) face of 6H—SiC, in Materials Science Forum, Vols. 338-342 (2000), p. 1101, S. Ogino, T. Oikawa and K. Ueno reported on the operation of a MOSFET formed using channel doping in which the dopant was implanted below the gate oxide layer, but did not report on results in cases in which channel doping was not used. Also, the report only described forming a gate oxide layer by dry oxidation in which the layer is dried in oxygen at 1100° C.
In Applied Physics Letters Vol. 77 (2000), p. 866, K. Fukuda, W. J. Cho, K. Arai, S. Suzuki, J. Senzaki and T. Tanaka reported, with respect to the relationship between interface trap density and a method of forming a gate oxide layer on the (000-1) face of 4H—SiC by thermal oxidation at 1200° C. However, they did not report on a method of forming a gate isulation layer at a temperature below 1200° C. and on the post-oxidation treatment.
As described in the foregoing, typically SiC has three faces: a (0001) face, a (11-20) face and a (000-1) face. The oxidation rate of the (11-20) face is higher than that of the (0001) face, and that of the (000-1) face is higher still. Specifically, the oxidation rate of the (000-1) face is some ten times higher than that of the (0001) face. Therefore, the optimum oxidation conditions and post-oxidation annealing conditions for decreasing the interface trap density at the oxidation layer/silicon carbide interface also differ from face to face. For example, in the case of the (0001) face, the interface trap density is lower when dry oxygen is used compared with when H2O is used, but in the case of the (11-20) face, the interface trap density is lower when H2O is used. The post-oxidation annealing effect also differs from face to face. Thus, the oxidation conditions and post-oxidation annealing conditions for minimizing the interface trap density have to be optimized for each face. In the initial research, SiC MOSFETs were formed on the (0001) face, but the channel mobility of such devices was no higher than 10 cm2/Vs. Recent reports describe channel mobility being improved to up to 110 cm2/Vs by reducing the interface trap density by using water to form a gate insulation layer on the (11-20) face of the SiC. However, the (11-20) face has lower dielectric breakdown field strength than the (0001) or (000-1) face, and is therefore disadvantageous for high-voltage-resistancehigh blocking voltage power devices. Also, there are no reports of MOSFETs fabricated on the (000-1) face operating without the use of channel doping technology. Channel doping is not suitable for high-voltage-resistancehigh blocking voltage power devices, because although it improves channel mobility, it causes leakage current to flow more readily, so voltage resistanceblocking voltage decreases.
In view of the above-described superiority of the properties of the (000-1) face compared with those of the (0001) and (11-20) faces, an object of the present invention is to provide a SiC semiconductor device with a (000-1) face silicon carbide substrate in which the device is given a high voltage resistancehigh blocking voltage and a high channel mobility by opting the method of heat-treatment used following gate oxide formation.